View HD66322T_4469529.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1557 HD66322T (64-level gray scale driver for high-quality tft liquid crystal display for xga and sxga) rev 0.0 november 1996 description the HD66322T is a tft-lcd source driver lsi, which is applicable to xga and sxga. the lsi receives 6-bit digital display data per pixel and outputs corresponding 64-level gray scale voltage. since the output circuit on this lsi incorporates an operational amplifier, a positive and a negative voltage can be alternately output from each output pin. therefore, a high-quality display with less crosstalk can be achieved without a complex circuit configuration. features high-speed operation ? maximum operating clock: 65 mhz (3.0v) operating voltage ? v cc = 3.0 to 3.6v ? vlcd = 10 0.5v lcd drive voltage ? low voltage: 0.2 ~vlcd/2 (v) ? high voltage: vlcd/2 ~ vlcdC0.2 (v) 384 lcd drive circuits multicolor display the HD66322T receives 6-bit digital display data per pixel, and selects and outputs an lcd drive voltage among 64-level gray scale voltages. when r, g, and b color filters are added to the lcd panel, a maximum of 260 thousand colors can be displayed. 36 data bits (six bits of gray scale code three dots of rgb two pixels) low output voltage deviation: voff = 10 mv (max)
HD66322T 1558 high-voltage asymmetrical drive counter electrode does not need to be converted into ac due to a 10-v wide dynamic range and alternate output of positive and negative voltages. in addition, as positive and negative voltages are generated from the reference voltage supplied from an external device, symmetrical or asymmetrical drive can be selected according to lcd characteristics. polarity inversion output to each pin inversion drive for each dot can be achieved even in a one-side location configuration due to alternate output of positive and negative voltages from each output pin; this achieves a high quality display with less crosstalk. operational amplifier an external reference voltage generator can be configured simply by adding a resistance ladder due to an operational amplifier incorporated in the output circuit of this lsi. bi-directional shift chip enable signal generator data polarity inversion bit can reduce current consumption when displaying white and black for each dot. package: tcp applicable system oa equipment such as an xga (1024 768 dots)-and an sxga (1280 1024 dots)-notebook personal computer or monitor pin arrangement y384 y383 y382 y381 y380 y379 y378 y377 y376 y9 y8 y7 y6 y5 y4 y3 y2 y1 note: this figure does not specify the tape carrier package dimensions. top view 1 2 3 4 5 6 7 8 9 10 eio2 d55 d54 d53 d52 d51 d50 d45 d44 d43 d42 d41 d40 d35 d34 d33 d32 d31 d30 testclk 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 test2 v cc test1 shl v9 v8 v7 v6 v5 vlcd 31 32 33 34 35 36 37 38 39 40 gnd2 v4 v3 v2 v1 v0 gnd1 cl2 cl1 m 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 d12 d11 d10 d05 d04 d03 d02 d01 d00 eio1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 pol d25 d24 d23 d22 d21 d20 d15 d14 d13 figure 1 pin arrangement
HD66322T 1559 block diagram clock control cl2 eio1 eio2 shl cl1 m latch address selector ....................... d55 to d50, d45 to d40, d35 to d30, d25 to d20, d15 to d10, and d05 to d00 6 planes 384-bit latch circuit (1) y1 y2 y3 y4 y384 vlcd v cc gnd 384-bit output amplifier 384-bit decoder v5, v6, v7, v8, and v9 v0, v1, v2, v3, and v4 64-level gray scale high voltage gray scale voltage generation data inversion circuit pol 64-level gray scale low voltage 384-bit latch circuit (2) .............................. .............................. 6 planes figure 2 block diagram block functions clock controller generates chip enable signals ( (,2 and (,2 ) and controls the internal timing signals. data inversion circuit inverts the polarity (when the pol signal is 1) or does not invert it (when the pol signal is 0) for input data.
HD66322T 1560 latch address selector generates latch signals, which sequentially trigger latch operation of input display data. latch circuit 1 latches 6-output 6-bit sequentially input display data; composed of 384 6 bits. latch circuit 2 latches 384 6-bit data latched in latch circuit 1 synchronously with the cl1 signal. decoder generates a 64-level gray scale voltage based on the lcd drive voltage (v8Cv0) and selects the lcd applicable voltage using the 6-bit data decoded signal. gray scale voltage generator generates a 64-level gray scale high voltage or a 64-level gray scale low voltage by dividing the external input voltage by resistance. output amplifier buffers and outputs the gray scale voltage selected for each output.
HD66322T 1561 pin functions table 1 pin functions signal name number s input/output function vlcd 1 power supply see figure 3. v cc 1 power supply gnd 1 power supply v9Cv5 5 power supply supplies power to the lcd applicable voltage generation circuit. voltage within the range of 5.7v to v ee must be applied to v0 to v4Cv0 5 v4 pins, and within the range of 0.2 to 5.0v to v5 to v9 pins. cl1 1 input while this clock is low, the lcd applicable voltage is output. cl2 1 input display data is stored at the falling edge of this signal. pol 1 input data polarity inversion signal, which saves the power supply of the data bus line in the interface. when this signal is high, display data is inverted in the driver, and when it is low, display data is input to the driver without being inverted. d55 to d50 d45 to d40 d35 to d30 d25 to d20 d15 to d10 d05 to d00 36 input inputs 6-bit (gray scale data) 6-pixel display data. (,2 (,2 2 input/output provides chip-enable signals. input or output depends on the shl signal. in shl = gnd, (,2 and (,2 are input and output, and in shl = v cc , (,2 and (,2 are output and input, respectively. at any one time, the signal being used for input must go low to enable the driver to latch display data, and the signal being used for output will be driven low after 312 pixels of data have been read. m 1 input an ac signal for controlling an lcd alternate drive. when this signal is 0, odd number pins (y1, y3, ..., y311) output the positive lcd applicable voltage and even number pins output the negative lcd applicable voltage, and when 1, vice versa. y1Cy384 384 output outputs lcd applicable voltages. test1.2 testclk 1 input a test pin. normally, this signal must be set low. shl 1 input selects the shift direction of display data. see figure 4.
HD66322T 1562 v cc ?nd: logic and low-voltage analog power supply vlcd?nd: high-voltage analog power supply gnd vlcd + + v cc figure 3 vlcd, v cc , and gnd power supply gnd d05 to d00 d15 to d10 d25 to d20 d35 to d30 d45 to d40 d55 to d50 1st last y1 y2 y3 y312 y310 y311 d55 to d50 d45 to d40 d35 to d30 d25 to d20 d15 to d10 d05 to d00 d55 to d50 d45 to d40 d35 to d30 d25 to d20 d15 to d10 d05 to d00 y4 y5 y6 y309 y307 y308 v cc d05 to d00 d15 to d10 d25 to d20 d35 to d30 d45 to d40 d55 to d50 last 1st y1 y2 y3 y312 y310 y311 d55 to d50 d45 to d40 d35 to d30 d25 to d20 d15 to d10 d05 to d00 d55 to d50 d45 to d40 d35 to d30 d25 to d20 d15 to d10 d05 to d00 y4 y5 y6 y309 y307 y308 figure 4 display data shift direction
HD66322T 1563 system overview figure 5 shows a block diagram of an xga (1024 768)-applicable tft color panel configured with multiple HD66322Ts. these HD66322Ts latch 6-bit data per dot, and select and output one level among 64 internally generated lcd-drive voltage levels of positive or negative polarity. when the pixels are structured using r, g, and b color filters, a maximum of 260 thousand colors can be displayed. in addition, the inversion drive for each row or for each dot can be achieved even though the HD66322Ts are located on one side as long as the inversion output function for each pin is used; this achieves a high- quality display. HD66322T no.1 HD66322T no.2 HD66322T no.8 384 384 384 scan driver 768 controller display data 36 (6 bits 6 pixels) control signals 3 (cl1, cl2, and m) lcd drive voltages 10 (v9?0) scan driver control signals 2 (flm and cl3) rgb tft color panel 260 thousand colors, 1024 768 dots counter electrode voltage 1 (vcom) scan driver voltages 2 (vgon and vgoff) lcd drive power supply circuit figure 5 system block diagram
HD66322T 1564 6-bit 6-dot digital data cl1 cl2 flm 1-frame period 512 1 768 1 1 horizontal period hv64 (v0?4) lv64 (v5?9) cl1 y1 y312 odd pin even pin hv64 hv64 hv64 hv64 lv64 lv64 lv64 lv64 lv64 lv64 hv64 hv64 note: hv64 means a 64-level gray scale high voltage, and lv64 means a 64-level gray scale low voltage. ..... --------- --------- --------- figure 6 timing chart (example of dot-inversion drive method)
HD66322T 1565 relationship between display data and output voltage the HD66322T outputs 64-level gray scale high voltage and 64-level gray scale low voltage generated by 10 levels of input lcd drive power supply voltage and 6-bit digital data. figure 7 shows the relationship among the input voltages from the lcd drive power supply circuit, digital codes, and output voltages. display data (6-bit digital data) power supply circuit HD66322T v9 v0 y1 y384 positive polarity 64 levels negative polarity 64 levels 10-v dynamic range ................ ..... figure 7 selection of lcd drive output level
HD66322T 1566 table 2 64-level gray scale high voltage display data di5 di4 di3 di2 di1 di0 64-level gray scale high voltage 111 111v4 1 1 1 1 1 0 v3 + 1819/2886 (v4 C v3) 1 1 1 1 0 1 v3 + 1286/2886 (v4 C v3) 1 1 1 1 0 0 v3 + 886/2886 (v4 C v3) 1 1 1 0 1 1 v3 + 619/2886 (v4 C v3) 1 1 1 0 1 0 v3 + 390/2886 (v4 C v3) 1 1 1 0 0 1 v3 + 190/2886 (v4 C v3) 111 000v3 1 1 0 1 1 1 v2 + 2535/2697 (v3 C v2) 1 1 0 1 1 0 v2 + 2377/2697 (v3 C v2) 1 1 0 1 0 1 v2 + 2217/2697 (v3 C v2) 1 1 0 1 0 0 v2 + 2084/2697 (v3 C v2) 1 1 0 0 1 1 v2 + 1951/2697 (v3 C v2) 1 1 0 0 1 0 v2 + 1818/2697 (v3 C v2) 1 1 0 0 0 1 v2 + 1707/2697 (v3 C v2) 1 1 0 0 0 0 v2 + 1600/2697 (v3 C v2) 1 0 1 1 1 1 v2 + 1500/2697 (v3 C v2) 1 0 1 1 1 0 v2 + 1400/2697 (v3 C v2) 1 0 1 1 0 1 v2 + 1300/2697 (v3 C v2) 1 0 1 1 0 0 v2 + 1200/2697 (v3 C v2) 1 0 1 0 1 1 v2 + 1100/2697 (v3 C v2) 1 0 1 0 1 0 v2 + 1000/2697 (v3 C v2) 1 0 1 0 0 1 v2 + 900/2697 (v3 C v2) 1 0 1 0 0 0 v2 + 800/2697 (v3 C v2) 1 0 0 1 1 1 v2 + 700/2697 (v3 C v2) 1 0 0 1 1 0 v2 + 600/2697 (v3 C v2) 1 0 0 1 0 1 v2 + 500/2697 (v3 C v2) 1 0 0 1 0 0 v2 + 400/2697 (v3 C v2) 1 0 0 0 1 1 v2 + 300/2697 (v3 C v2) 1 0 0 0 1 0 v2 + 200/2697 (v3 C v2) 1 0 0 0 0 1 v2 + 100/2697 (v3 C v2) 100 000v2
HD66322T 1567 table 2 64-level gray scale high voltage (cont) display data di5 di4 di3 di2 di1 di0 64-level gray scale high voltage 0 1 1 1 1 1 v1 + 3322/3422 (v2 C v1) 0 1 1 1 1 0 v1 + 3222/3422 (v2 C v1) 0 1 1 1 0 1 v1 + 3122/3422 (v2 C v1) 0 1 1 1 0 0 v1 + 3015/3422 (v2 C v1) 0 1 1 0 1 1 v1 + 2904/3422 (v2 C v1) 0 1 1 0 1 0 v1 + 2793/3422 (v2 C v1) 0 1 1 0 0 1 v1 + 2682/3422 (v2 C v1) 0 1 1 0 0 0 v1 + 2571/3422 (v2 C v1) 0 1 0 1 1 1 v1 + 2460/3422 (v2 C v1) 0 1 0 1 1 0 v1 + 2349/3422 (v2 C v1) 0 1 0 1 0 1 v1 + 2238/3422 (v2 C v1) 0 1 0 1 0 0 v1 + 2127/3422 (v2 C v1) 0 1 0 0 1 1 v1 + 1994/3422 (v2 C v1) 0 1 0 0 1 0 v1 + 1861/3422 (v2 C v1) 0 1 0 0 0 1 v1 + 1728/3422 (v2 C v1) 0 1 0 0 0 0 v1 + 1595/3422 (v2 C v1) 0 0 1 1 1 1 v1 + 1435/3422 (v2 C v1) 0 0 1 1 1 0 v1 + 1275/3422 (v2 C v1) 0 0 1 1 0 1 v1 + 1115/3422 (v2 C v1) 0 0 1 1 0 0 v1 + 925/3422 (v2 C v1) 0 0 1 0 1 1 v1 + 725/3422 (v2 C v1) 0 0 1 0 1 0 v1 + 496/3422 (v2 C v1) 0 0 1 0 0 1 v1 + 267/3422 (v2 C v1) 001 000v1 0 0 0 1 1 1 v0 + 3733/4000 (v1 C v0) 0 0 0 1 1 0 v0 + 3333/4000 (v1 C v0) 0 0 0 1 0 1 v0 + 2933/4000 (v1 C v0) 0 0 0 1 0 0 v0 + 2533/4000 (v1 C v0) 0 0 0 0 1 1 v0 + 2000/4000 (v1 C v0) 0 0 0 0 1 0 v0 + 1467/4000 (v1 C v0) 0 0 0 0 0 1 v0 + 800/4000 (v1 C v0) 000 000v0
HD66322T 1568 table 3 64-level gray scale low voltage display data di5 di4 di3 di2 di1 di0 64-level gray scale low voltage 111 111v5 1 1 1 1 1 0 v6 + 1819/2886 (v5 C v6) 1 1 1 1 0 1 v6 + 1286/2886 (v5 C v6) 1 1 1 1 0 0 v6 + 886/2886 (v5 C v6) 1 1 1 0 1 1 v6 + 619/2886 (v5 C v6) 1 1 1 0 1 0 v6 + 390/2886 (v5 C v6) 1 1 1 0 0 1 v6 + 190/2886 (v5 C v6) 111 000v6 1 1 0 1 1 1 v7 + 2537/2697 (v6 C v7) 1 1 0 1 1 0 v7 + 2377/2697 (v6 C v7) 1 1 0 1 0 1 v7 + 2217/2697 (v6 C v7) 1 1 0 1 0 0 v7 + 2084/2697 (v6 C v7) 1 1 0 0 1 1 v7 + 1951/2697 (v6 C v7) 1 1 0 0 1 0 v7 + 1818/2697 (v6 C v7) 1 1 0 0 0 1 v7 + 1707/2697 (v6 C v7) 1 1 0 0 0 0 v7 + 1600/2697 (v6 C v7) 1 0 1 1 1 1 v7 + 1500/2697 (v6 C v7) 1 0 1 1 1 0 v7 + 1400/2697 (v6 C v7) 1 0 1 1 0 1 v7 + 1300/2697 (v6 C v7) 1 0 1 1 0 0 v7 + 1200/2697 (v6 C v7) 1 0 1 0 1 1 v7 + 1100/2697 (v6 C v7) 1 0 1 0 1 0 v7 + 1000/2697 (v6 C v7) 1 0 1 0 0 1 v7 + 900/2697 (v6 C v7) 1 0 1 0 0 0 v7 + 800/2697 (v6 C v7) 1 0 0 1 1 1 v7 + 700/2697 (v6 C v7) 1 0 0 1 1 0 v7 + 600/2697 (v6 C v7) 1 0 0 1 0 1 v7 + 500/2697 (v6 C v7) 1 0 0 1 0 0 v7 + 400/2697 (v6 C v7) 1 0 0 0 1 1 v7 + 300/2697 (v6 C v7) 1 0 0 0 1 0 v7 + 200/2697 (v6 C v7) 1 0 0 0 0 1 v7 + 100/2697 (v6 C v7) 100 000v7
HD66322T 1569 table 3 64-level gray scale low voltage (cont) display data di5 di4 di3 di2 di1 di0 64-level gray scale low voltage 0 1 1 1 1 1 v8 + 3322/3422 (v7 C v8) 0 1 1 1 1 0 v8 + 3222/3422 (v7 C v8) 0 1 1 1 0 1 v8 + 3122/3422 (v7 C v8) 0 1 1 1 0 0 v8 + 3015/3422 (v7 C v8) 0 1 1 0 1 1 v8 + 2904/3422 (v7 C v8) 0 1 1 0 1 0 v8 + 2793/3422 (v7 C v8) 0 1 1 0 0 1 v8 + 2682/3422 (v7 C v8) 0 1 1 0 0 0 v8 + 2571/3422 (v7 C v8) 0 1 0 1 1 1 v8 + 2460/3422 (v7 C v8) 0 1 0 1 1 0 v8 + 2349/3422 (v7 C v8) 0 1 0 1 0 1 v8 + 2238/3422 (v7 C v8) 0 1 0 1 0 0 v8 + 2127/3422 (v7 C v8) 0 1 0 0 1 1 v8 + 1994/3422 (v7 C v8) 0 1 0 0 1 0 v8 + 1861/3422 (v7 C v8) 0 1 0 0 0 1 v8 + 1728/3422 (v7 C v8) 0 1 0 0 0 0 v8 + 1595/3422 (v7 C v8) 0 0 1 1 1 1 v8 + 1435/3422 (v7 C v8) 0 0 1 1 1 0 v8 + 1275/3422 (v7 C v8) 0 0 1 1 0 1 v8 + 1115/3422 (v7 C v8) 0 0 1 1 0 0 v8 + 925/3422 (v7 C v8) 0 0 1 0 1 1 v8 + 725/3422 (v7 C v8) 0 0 1 0 1 0 v8 + 496/3422 (v7 C v8) 0 0 1 0 0 1 v8 + 267/3422 (v7 C v8) 001 000v8 0 0 0 1 1 1 v9 + 3733/4000 (v8 C v9) 0 0 0 1 1 0 v9 + 3333/4000 (v8 C v9) 0 0 0 1 0 1 v9 + 2933/4000 (v8 C v9) 0 0 0 1 0 0 v9 + 2533/4000 (v8 C v9) 0 0 0 0 1 1 v9 + 2000/4000 (v8 C v9) 0 0 0 0 1 0 v9 + 1467/4000 (v8 C v9) 0 0 0 0 0 1 v9 + 800/4000 (v8 C v9) 000 000v9
HD66322T 1570 relationship between input data and output voltage the HD66322T outputs gray scale voltages whose polarities are different at odd number output pins and even number output pins with respect to the lcd counter-electrode voltage. the relationship between input data and output pins is shown in figure 8 for the following conditions: vlcdC0.2 3 v0 3 v1 3 v2 3 v3 3 v4 3 vlcd/2, and vlcd/2 3 v5 3 v6 3 v7 3 v8 3 v9 3 0.2v input data v8 000000 000111 111111 msb lsb v7 v6 v5 low-voltage output 011111 110111 high-voltage output v9 v3 v2 v1 v0 v4 vcom figure 8 relationship between input data and output voltages
HD66322T 1571 inversion drive for each output pin the HD66322T generates a 64-level positive- or negative-polarity grayscale voltage with respect to the inversion reference voltage for each adjacent odd and even number output pin. in addition, the lcd ac drive can be controlled by switching the polarity of the m signal (refer to the section on pin functions). thus, if the HD66322Ts are located on one side of the tft lcd panel, a dot inversion drive, which can apply the grayscale voltage with the opposite polarity to each adjacent dot, can be performed by switching the polarity of the m signal for each cl1 input. this can decrease crosstalk degrading display quality and achieve a high-quality display. HD66322T HD66322T gate driver HD66322T HD66322T gate driver odd frame even frame figure 9 dot-inversion drive
HD66322T 1572 absolute maximum ratings item symbol ratings unit note power supply voltage logic circuit (low voltage) v cc C0.3 to + 5.0 v 1 lcd drive circuit (high voltage) vlcd C 0.3 to + 12.0 v 1 input voltage (high voltage) v t1 C0.3 to v lcd + 0.3 v 1 and 2 input voltage (low voltage) v t2 C0.3 to v cc + 0.3 v 1, 3, and 4 operating temperature topr C20 to +75 c storage temperature tstg C40 to +125 c notes: if the lsi is used beyond the above maximum ratings, it may be permanently damaged. it should always be used within its specified operating range for normal operation to prevent malfunction or degraded reliability. 1. assuming gnd = 0v. 2. applies to input pins cl1, cl2, shl, dxx, m, and pol, and i/o pins (,2 and (,2 when used as input. 3. specifies voltage to be input to the lcd drive power supply pins. either of the following relationships must be held: v lcd C0.2 3 v0 3 v1 3 v2 3 v3 3 v4 3 v lcd /2 and v lcd /2 3 v5 3 v6 3 v7 3 v8 3 v9 3 0.2v, or v lcd C0.2 3 v4 3 v3 3 v2 3 v1 3 v0 3 v lcd /2 and v lcd /2 3 v9 3 v8 3 v7 3 v6 3 v5 3 0.2v 4. the following relationship must be held for the electrical potentials of v9 to v5 and v4 to v0. vin C v n+1 1v (n = 0 to 3 or 5 to 8)
HD66322T 1573 electrical characteristics dc characteristics (v cc Cgnd = 3.0 to 3.6v, vlcdCgnd = 9.5 ~ 10.5v, and ta = C20 to +75 c, unless otherwise stated) item symbol applicable pin min. typ. max. unit conditions note input high level voltage v ih cl1, cl2, shl, dij, m, pol, eio1 (i), 0.7 v cc v cc v input low level voltage v il and eio2 (i) 0 0.3 v cc v output high level voltage v oh eio1 (o) and eio2 (o) v cc C 0.4 v i oh = C0.4 ma output low level voltage v ol 0.4 v i ol = 0.4 ma input leakage current (1) i il1 cl1, cl2, shl, dij, m, and pol C5 +5 m a input leakage current (2) i il2 eio1 (i) and eio2 (i) C10 +10 m a output offset voltage voff y1 to y312 10 mv v ee = 13v f cl1 = 53.8 khz (1 horizontal = 18.6 m s) 1 logic unit consumptive current i cc v cc 4.5 ma v cc = 3.3v v lcd = 10v f cl1 = 71.7 khz 2 standby consumptive current i st v cc 0.7 ma (1 horizontal = 14 m s) f cl2 = 65 mhz lcd drive power supply voltage (2) i lcd v lcd 4.5 ma notes: 1 output offset voltage voff is defined as difference between the actual output voltage and output voltage expected. 2. except for the current flowing in v0 to v9; outputs are unloaded.
HD66322T 1574 ac characteristics (v cc Cgnd = 3.0 to 3.6v, vlcdCgnd = 9.5 ~ 10.5v, and ta = C20 to +75 c, unless otherwise stated) item symbol applicable pins min. typ. max. unit conditions note clock cycle time f max cl2 65 mhz clock high level width t cwh cl2 7 ns clock low level width t cwl cl2 7 ns clock rise time t r cl1 and cl2 4 ns clock fall time t f cl1 and cl2 4 ns clock setup time t su cl1 and cl2 50 ns clock hold time t h cl1 and cl2 300 ns data setup time t dsu dij and cl2 3 ns data hold time t dh dij and cl2 3 ns pol setup time t psu pol and cl2 3 ns pol hold time t ph pol and cl2 3 ns m setup time t msu m and cl2 100 ns m hold time t mh m and cl1 200 ns enable setup time t esu eio1, eio2, and cl2 0 ns enable output delay time t ed eio1, eio2, and cl2 30 ns 1 cl1 high level width t cl1wh cl1 56 ns driver output delay time t dd cl1 and y1 to y384 10 m s vlcd = 10v ta = 25 c 2 notes: 1. the load conditions of an enable output pin are shown in figure 13. 2. defined under the conditions shown in figure 14.
HD66322T 1575 t cwh t cwl 1/fmax t dsu t dh dij, pol cl2 0.7v cc 0.3v cc 0.7v cc 0.3v cc 0.5v cc 0.5v cc 0.5v cc 0.7v cc 0.3v cc 0.3v cc t r t dd fixed voltage 5% y1?384 t cl1wh t su t h ted tesu cl2 cl1 enable output enable input 0.7v cc 0.3v cc 0.3v cc 0.3v cc 0.3v cc 0.3v cc 0.3v cc 0.8v cc 1 626364 m t mh t msu t psu t ph fixed voltage 95% t f figure 10 ac characteristics
HD66322T 1576 30 pf enable output figure 11 load conditions of enable output pin y1?384 25 k w 30 pf 30 pf 25 k w figure 12 load conditions for definition of driver output delay time

▲Up To Search▲

Price & Availability of HD66322T

	To Download HD66322T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .